1. Technical Field
The present invention relates generally to a semiconductor integrated circuit, and more particularly to the sense amplifier control circuit of a semiconductor memory device.
2. Related Art
The data output operations of a semiconductor memory device are performed as follows in general. The cell data selected through a word line is amplified by a bit line sense amplifier (BLSA), and the amplified data is loaded onto a global input/output (GIO) line and outputted to an I/O terminal.
When the data from the cells that are connected to a selected word line is loaded onto a bit line pair (BL pair) comprised of a bit line BL and a bit bar line BLb, a sense amplifier enable signal (which signal is used to indicate the time at which the operation of the BLSA would start) is enabled, so as to drive a sense amplifier control circuit. Furthermore, the bias voltage of the BLSA shifts to a core voltage VCORE and a ground voltage VSS by the sense amplifier control circuit, so as to drive a sense amplifier latch. That is, when the sense amplifier latch starts operating, the voltages of the BL pair (BL and BLb) that used to maintain a minute voltage difference shift to the core voltage VCORE and the ground voltage VSS, respectively. The cell data amplified as described above is loaded onto the GIO line and is outputted to the I/O terminal.
FIG. 1 relates to a conventional semiconductor memory device.
FIG. 1 shows the structure of a conventional semiconductor memory device.
The known semiconductor memory device as shown in FIG. 1 includes a plurality of cell arrays 10˜15, a plurality of sub-word line driver (SWD) arrays 20˜23, a plurality of BLSA arrays 30˜32, and a plurality of sub-holes 40 and 41.
The plurality of sub-holes 40 and 41 includes respective sense amplifier control circuits 40˜1 and 41˜1.
The plurality of BLSA arrays 30˜32 includes a plurality of BLSAs 50˜58.
Each of the plurality of cell arrays 10˜15 includes a plurality of cells for storing data. Each pair of cell arrays (e.g., placed vertically in FIG. 1) among the cell arrays 10˜15, share one of the BLSA arrays 30˜32 (e.g., horizontally disposed in FIG. 1). Each of the BLSA arrays 30˜32 includes a plurality of the BLSAs to amplify a minute voltage difference between the bit line BL and the bit bar line BLb. Furthermore, the regions of cell arrays placed horizontally, from among the cell arrays 10˜15, share one of the SWD arrays 20˜23 vertically disposed. The SWD arrays 20˜23 include a plurality of word line drivers to selectively drive the plurality of cell arrays 10˜15 when an address is received.
The sense amplifier control circuits 40˜1 and 41˜1 are placed in the respective sub-holes 40 and 41.
The sub-holes are placed in the respective regions where the BLSA arrays horizontally disposed between upper and lower cell arrays cross SWD arrays vertically disposed between left and right cell arrays. That is, the sub-hole refers to a space unoccupied after the BLSA arrays and the SWD arrays are placed in the X-axis and Y-axis directions. The sub-hole includes the sense amplifier control circuit to supply voltage to the BLSAs to amplify the voltage difference.
The area of a cell array region will need to increase in order to increase the yield of semiconductor memory devices. Then, the resulting lengths of the lines to couple the BLSAs in the BLSA array and the sense amplifier control circuit in the sub-hole will also have to increase. The BLSA array region would relatively increase in the X-axis direction in proportion to the increase of the cell array region. Since the BLSAs and the sense amplifier control circuit to supply voltage to the BLSAs are separately placed in the BLSA array region and the sub-hole region, the length of connection between the BLSAs and the sense amplifier control circuit increases depending on the positions of the BLSAs. The voltage supplied from the sense amplifier control circuit results in a noise and a consequent problem of a reduction in the operation margin of the BLSA caused by the noise in the voltage supplied from the sense amplifier control circuit.